Power-Adaptive Network Processors

This paper explores the notion of dynamically scaling the architectural resources of network processor systems with the aim reducing their overall power consumption levels. We show that when faced with a realistic traffic load characterized by a high degree of burstiness, a network processor architecture wastes a non-trivial fraction of total power consumed. We then suggest a simple software approach for reducing power consumption based on the selective shutdown of processing units during periods of low activity on the link, and evaluate it in terms of both the power savings achieved and performance costs incurred. Our results suggest that significant power savings can be realized with generally tolerable degradations in throughput and latency, resulting in considerable increases in the overall energy efficiency of the device.